# -------------------------------------------------------------------------- # # # Copyright (C) 2018 Intel Corporation. All rights reserved. # Your use of Intel Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Intel Program License # Subscription Agreement, the Intel Quartus Prime License Agreement, # the Intel FPGA IP License Agreement, or other applicable license # agreement, including, without limitation, that your use is for # the sole purpose of programming logic devices manufactured by # Intel and sold by Intel or its authorized distributors. Please # refer to the applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus Prime # Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition # Date created = 20:17:15 July 23, 2020 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # qc5_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus Prime software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*qc5_pll50*|altera_pll:altera_pll_i*|*" set_instance_assignment -name PLL_AUTO_RESET ON -to "*qc5_pll50*|altera_pll:altera_pll_i*|*" set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*qc5_pll50*|altera_pll:altera_pll_i*|*" set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*qc5_pll66*|altera_pll:altera_pll_i*|*" set_instance_assignment -name PLL_AUTO_RESET ON -to "*qc5_pll66*|altera_pll:altera_pll_i*|*" set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*qc5_pll66*|altera_pll:altera_pll_i*|*" set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*qc5_pll75*|altera_pll:altera_pll_i*|*" set_instance_assignment -name PLL_AUTO_RESET ON -to "*qc5_pll75*|altera_pll:altera_pll_i*|*" set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*qc5_pll75*|altera_pll:altera_pll_i*|*" set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*qc5_pll100*|altera_pll:altera_pll_i*|*" set_instance_assignment -name PLL_AUTO_RESET ON -to "*qc5_pll100*|altera_pll:altera_pll_i*|*" set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*qc5_pll100*|altera_pll:altera_pll_i*|*" set_location_assignment PIN_M9 -to qc5_clock_50 set_location_assignment PIN_Y9 -to qc5_dram_addr[12] set_location_assignment PIN_T9 -to qc5_dram_addr[11] set_location_assignment PIN_R6 -to qc5_dram_addr[10] set_location_assignment PIN_W8 -to qc5_dram_addr[9] set_location_assignment PIN_T8 -to qc5_dram_addr[8] set_location_assignment PIN_U8 -to qc5_dram_addr[7] set_location_assignment PIN_V6 -to qc5_dram_addr[6] set_location_assignment PIN_U7 -to qc5_dram_addr[5] set_location_assignment PIN_U6 -to qc5_dram_addr[4] set_location_assignment PIN_N6 -to qc5_dram_addr[3] set_location_assignment PIN_N8 -to qc5_dram_addr[2] set_location_assignment PIN_P7 -to qc5_dram_addr[1] set_location_assignment PIN_P8 -to qc5_dram_addr[0] set_location_assignment PIN_P9 -to qc5_dram_ba[1] set_location_assignment PIN_T7 -to qc5_dram_ba[0] set_location_assignment PIN_AA7 -to qc5_dram_cas_n set_location_assignment PIN_V9 -to qc5_dram_cke set_location_assignment PIN_AB11 -to qc5_dram_clk set_location_assignment PIN_AB5 -to qc5_dram_cs_n set_location_assignment PIN_P12 -to qc5_dram_dq[15] set_location_assignment PIN_R12 -to qc5_dram_dq[14] set_location_assignment PIN_U12 -to qc5_dram_dq[13] set_location_assignment PIN_R11 -to qc5_dram_dq[12] set_location_assignment PIN_R10 -to qc5_dram_dq[11] set_location_assignment PIN_U11 -to qc5_dram_dq[10] set_location_assignment PIN_T10 -to qc5_dram_dq[9] set_location_assignment PIN_U10 -to qc5_dram_dq[8] set_location_assignment PIN_AA8 -to qc5_dram_dq[7] set_location_assignment PIN_AB8 -to qc5_dram_dq[6] set_location_assignment PIN_AA9 -to qc5_dram_dq[5] set_location_assignment PIN_Y10 -to qc5_dram_dq[4] set_location_assignment PIN_AB10 -to qc5_dram_dq[3] set_location_assignment PIN_AA10 -to qc5_dram_dq[2] set_location_assignment PIN_Y11 -to qc5_dram_dq[1] set_location_assignment PIN_AA12 -to qc5_dram_dq[0] set_location_assignment PIN_AB7 -to qc5_dram_ldqm set_location_assignment PIN_AB6 -to qc5_dram_ras_n set_location_assignment PIN_V10 -to qc5_dram_udqm set_location_assignment PIN_W9 -to qc5_dram_we_n set_location_assignment PIN_AB13 -to qc5_button[1] set_location_assignment PIN_D17 -to qc5_led[0] set_location_assignment PIN_V18 -to qc5_button[0] set_location_assignment PIN_AA1 -to qc5_uart_txd set_location_assignment PIN_W2 -to qc5_uart_rxd set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_addr[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_addr[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_addr[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_addr[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_addr[4] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_addr[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_addr[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_addr[7] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_addr[8] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_addr[9] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_addr[10] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_addr[11] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_addr[12] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_ba[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_ba[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_cas_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_cke set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_clk set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_cs_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[4] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[7] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[8] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[9] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[10] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[11] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[12] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[13] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[14] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_dq[15] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_ldqm set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_ras_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_udqm set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_dram_we_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_uart_txd set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qc5_uart_rxd set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CEFA2F23C7 set_global_assignment -name TOP_LEVEL_ENTITY qc5 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:17:15 JULY 23, 2020" set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Standard Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 set_global_assignment -name VERILOG_MACRO "LSI11_DEPTH_MICROM=(* max_depth = 1024 *)" set_global_assignment -name VERILOG_MACRO "LSI11_FILE_MICROM=\"..\\\\..\\\\..\\\\lsi\\\\rom\\\\all_22b.rom\"" set_global_assignment -name VERILOG_MACRO "M4_FILE_MICROM=\"..\\\\..\\\\..\\\\am4\\\\rom\\\\mc.rom\"" set_global_assignment -name VERILOG_MACRO "F11_FILE_MICROM_000=\"..\\\\..\\\\..\\\\f11\\\\rom\\\\000.rom\"" set_global_assignment -name VERILOG_MACRO "F11_FILE_MICROM_001=\"..\\\\..\\\\..\\\\f11\\\\rom\\\\001.rom\"" set_global_assignment -name VERILOG_MACRO "F11_FILE_MICROM_002=\"..\\\\..\\\\..\\\\f11\\\\rom\\\\002.rom\"" set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 set_global_assignment -name VERILOG_FILE ../../lib/config.v set_global_assignment -name VERILOG_FILE ../rtl/qc5_top.v set_global_assignment -name VERILOG_FILE ../rtl/qc5_alib.v set_global_assignment -name VERILOG_FILE ../rtl/vm1_alib.v set_global_assignment -name VERILOG_FILE ../rtl/vm3_alib.v set_global_assignment -name VERILOG_FILE ../rtl/f11_alib.v set_global_assignment -name MIF_FILE ../../lib/vm1_reg.mif set_global_assignment -name VERILOG_FILE ../../lib/wbc_vic.v set_global_assignment -name VERILOG_FILE ../../lib/wbc_uart.v set_global_assignment -name VERILOG_FILE ../../lib/wbc_rst.v set_global_assignment -name VERILOG_FILE ../../lib/wbc_vm1.v set_global_assignment -name VERILOG_FILE ../../lib/wbc_vm2.v set_global_assignment -name VERILOG_FILE ../../lib/wbc_vm3.v set_global_assignment -name VERILOG_FILE ../../lib/wbc_lsi.v set_global_assignment -name VERILOG_FILE ../../lib/wbc_am4.v set_global_assignment -name VERILOG_FILE ../../lib/wbc_f11.v set_global_assignment -name VERILOG_FILE ../../../vm1/hdl/wbc/rtl/vm1_wb.v set_global_assignment -name VERILOG_FILE ../../../vm1/hdl/wbc/rtl/vm1_plm.v set_global_assignment -name VERILOG_FILE ../../../vm1/hdl/wbc/rtl/vm1_tve.v set_global_assignment -name VERILOG_FILE ../../../vm2/hdl/wbc/rtl/vm2_wb.v set_global_assignment -name VERILOG_FILE ../../../vm2/hdl/wbc/rtl/vm2_plm.v set_global_assignment -name VERILOG_FILE ../../../vm3/hdl/wbc/rtl/vm3_wb.v set_global_assignment -name VERILOG_FILE ../../../vm3/hdl/wbc/rtl/vm3_plm.v set_global_assignment -name VERILOG_FILE ../../../lsi/hdl/wbc/rtl/lsi_wb.v set_global_assignment -name VERILOG_FILE ../../../lsi/hdl/wbc/rtl/mcp_plm.v set_global_assignment -name VERILOG_FILE ../../../lsi/hdl/wbc/rtl/mcp1611.v set_global_assignment -name VERILOG_FILE ../../../lsi/hdl/wbc/rtl/mcp1621.v set_global_assignment -name VERILOG_FILE ../../../lsi/hdl/wbc/rtl/mcp1631.v set_global_assignment -name VERILOG_FILE ../../../am4/hdl/wbc/rtl/am4_wb.v set_global_assignment -name VERILOG_FILE ../../../am4/hdl/wbc/rtl/am4_seq.v set_global_assignment -name VERILOG_FILE ../../../am4/hdl/wbc/rtl/am4_plm.v set_global_assignment -name VERILOG_FILE ../../../am4/hdl/wbc/rtl/am4_mcrom.v set_global_assignment -name VERILOG_FILE ../../../am4/hdl/wbc/rtl/am4_alu.v set_global_assignment -name VERILOG_FILE ../../../f11/hdl/wbc/rtl/dc_302.v set_global_assignment -name VERILOG_FILE ../../../f11/hdl/wbc/rtl/dc_303.v set_global_assignment -name VERILOG_FILE ../../../f11/hdl/wbc/rtl/dc_304.v set_global_assignment -name VERILOG_FILE ../../../f11/hdl/wbc/rtl/dc_fpp.v set_global_assignment -name VERILOG_FILE ../../../f11/hdl/wbc/rtl/dc_pla.v set_global_assignment -name VERILOG_FILE ../../../f11/hdl/wbc/rtl/dc_pla_0.v set_global_assignment -name VERILOG_FILE ../../../f11/hdl/wbc/rtl/dc_pla_1.v set_global_assignment -name VERILOG_FILE ../../../f11/hdl/wbc/rtl/dc_pla_2.v set_global_assignment -name VERILOG_FILE ../../../f11/hdl/wbc/rtl/dc_rom.v set_global_assignment -name VERILOG_FILE ../../../f11/hdl/wbc/rtl/f11_wb.v set_global_assignment -name MIF_FILE ../../../am4/rom/mc.mif set_global_assignment -name MIF_FILE ../../../f11/rom/000.mif set_global_assignment -name MIF_FILE ../../../f11/rom/001.mif set_global_assignment -name MIF_FILE ../../../f11/rom/002.mif set_global_assignment -name MIF_FILE ../../tst/lsi.mif set_global_assignment -name MIF_FILE ../../tst/vm1.mif set_global_assignment -name MIF_FILE ../../tst/vm2.mif set_global_assignment -name MIF_FILE ../../tst/vm3.mif set_global_assignment -name MIF_FILE ../../tst/am4.mif set_global_assignment -name MIF_FILE ../../tst/f11.mif set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top